1. Field of the Invention
This invention relates generally to the replacement of defective memory cells in a semiconductor memory, and, more particularly, to the replacement of defective memory cells using a built-in self-test mechanism.
2. Description of the Related Art
A semiconductor memory device typically includes an array of memory cells, and the array is normally divided into a number of sub-arrays. Memory cells in the array are selected for reading and writing by means of row and column address signals input to the semiconductor memory device. The row and column address signals are processed by address decoding circuitry to select row lines and column lines in the array to access the desired memory cell or memory cells. A common practice in semiconductor memory devices is to implement the decoding at more than one level. For example, a first level decoding may yield data from a plurality of memory cells in the array, while a second level of decoding will select one memory cell, or a subset of memory cells, from the plurality. Thus, an address input to a semiconductor memory device will commonly result in the selection of a plurality of memory cells in the array or sub-array of the memory device, at least at a first level of decoding. That is, a plurality of memory cells will typically be selected by, or respond to, any particular address.
When semiconductor devices are manufactured, defective memory cells may occur in the memory array or in a sub-array. To salvage the semiconductor memory device despite these defective memory cells, and thus to increase overall yield in the manufacturing process, redundancy is commonly implemented. Redundant memory elements are located throughout the memory array, and each sub-array in the memory array will typically have associated with it a plurality of redundant memory elements. When a defective memory cell is detected in a sub-array, redundant decoding circuitry associated with the redundant memory elements for that sub-array may be programmed to respond to the address of the defective memory cell. When the address of the defective memory cell is input to the sub-array, the redundant memory element will respond in place of the defective memory cell. Redundancy and various methods for its implementation are known to those of ordinary skill in the art.
Redundant memory elements generally comprise redundant rows and/or redundant columns. When a defective memory cell is located, the row (or column) on which it is located may be replaced with a redundant row (or column) by programming, or otherwise altering, the row and column decoding circuitry. If a row in the memory array or sub-array contains two or more defective memory cells (each being on a different column), a single redundant row will suffice to "repair" the multiple "bad bits." If a row in the memory array contains a single defective memory cell, either a redundant row or a redundant column may be used to replace the row or column containing the defective memory cell. During testing of memory arrays, numerous defective memory cells may be encountered, and the replacement of defective cells using a limited number of redundant rows and columns becomes complex. Unless the defective cells can be replaced, the memory array will be unsuitable. Moreover, in certain circumstances, a memory cell may be evaluated as defective at one time, whereas during a subsequent task, that memory cell may be evaluated as non-defective. Hence, the process of detecting and replacing defective memory cells has become extremely complex, particularly in view of the ever-increasing numbers of memory cells in memory arrays.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.